1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a memory apparatus including nonvolatile memory cells and a semiconductor system using the same.
2. Related Art
In general, a DRAM includes a memory cell constituted by a capacitor, and data is stored by charging or discharging the capacitor of the memory cell. However, since the capacitor has a leakage due to the characteristics thereof, the DRAM has a disadvantage in that it is a volatile memory. In order to overcome the disadvantage, memories which are nonvolatile and do not need the refreshing of data have been developed. In particular, attempts have continuously been made to realize nonvolatility by modifying the structure of a memory cell. One of these attempts is a resistive memory apparatus which includes a resistive memory cell.
A resistive memory apparatus includes a memory cell which is formed of a variable resistance substance, and the variable resistance substance may have a resistance value that is changed according to the magnitude of current flowing through it. Accordingly, by controlling the magnitude of current to be applied to the memory cell, desired data may be written in the memory cell. For instance, in the case where the memory cell is a high resistance state, the memory cell may have stored data of 0, and, in the case where the memory cell is a low resistance state, the memory cell may have stored data of 1. The variable resistance substance may have at least three resistance states. Therefore, the memory cell of the resistive memory apparatus may be utilized as a multi-level cell capable of storing multi-bit data.
FIG. 1 is a diagram schematically showing the configuration of a conventional resistive memory apparatus 10. In FIG. 1, the resistive memory apparatus 10 includes a memory cell array 11, a row decoding unit 12, a column decoding unit 13, and a read driver 14. In the memory cell array 11, a plurality of word lines including WL0 to WL2 and a plurality of bit lines including BL0 to BL2 are disposed, and memory cells MC are electrically coupled to the crossing points of the word lines and the bit lines. The row decoding unit 12 selects a word line to access, in response to a row address, and the column decoding unit 13 selects a bit line to access, in response a column address. Accordingly, as a specified word line and a specified bit line are selected, a specified memory cell MC may be accessed.
The read driver 14 applies sensing current and/or a voltage to the accessed memory cell MC in a read operation. By sensing a voltage and/or current which changes according to the resistance value of the memory cell MC, it is possible to read the data stored in the memory cell MC. In the case where the memory cell MC is a multi-level cell, in order to precisely read the multi-bit data stored in the memory cell MC, the read driver 14 may include an analog-to-digital converter (ADC).